`timescale 1ns / 10ps
`define clock_period 20

module bubble_sort_demo_tb;

	reg[3:0] a;
	reg[3:0] b;
	reg[3:0] c;
	reg[3:0] d;
	wire[3:0] outa;
	wire[3:0] outb;
	wire[3:0] outc;
	wire[3:0] outd;

	bubble_sort_demo sort0(
		.A(a),
		.B(b),
		.C(c),
		.D(d),
		.Outa(outa),
		.Outb(outb),
		.Outc(outc),
		.Outd(outd)
	);
	
	initial begin
		
		a = 4'd4;
		b = 4'd3;
		c = 4'd2;
		d = 4'd1;
		
		#(`clock_period)
		
		a = 4'd5;
		b = 4'd2;
		c = 4'd7;
		d = 4'd1;
		
		#(`clock_period)
		
		$stop;
		
	end

endmodule
